Regviz

Silicon Labs /SiM3_NRND /SIM3L168_A /UART_0 /CLKDIV

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLKDIV

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/SiM3_NRND/SIM3L168_A/UART_0/CLKDIV#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DIV1)CLKDIV

CLKDIV=DIV1

Description

Clock Divider

Fields

CLKDIV

Clock Divider.

0 (DIV1): Divide by 1.

1 (DIV2): Divide by 2.

2 (DIV4): Divide by 4.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data